1. Field of the Invention
The present invention relates to a wiring board and a manufacturing method thereof. More particularly, the present invention relates to a wiring board and a manufacturing method thereof which are suitable for mounting, for example, peripheral pad type semiconductor integrated circuit elements by flip-chip bonding.
2. Description of Related Art
Examples of semiconductor integrated circuit elements of related art include so-called peripheral pad type semiconductor integrated circuit elements with a large number of electrode terminals arranged along the outer periphery of one major surface thereof. An example of the method of mounting these semiconductor integrated circuit elements on a wiring board is a flip-chip bonding method. In the flip-chip bonding method, firstly, part of wiring conductors for connecting semiconductor elements mounted on a wiring board is exposed correspondingly to the arrangement of the electrode terminals of the semiconductor integrated circuit elements. Secondly, the exposed part of the wiring conductors for connecting the semiconductor elements is opposed to the electrode terminals of the semiconductor integrated circuit elements, and then electrically connected to each other through, for example, solder bumps.
As shown in FIGS. 12-14, a wiring board 120 of related art (designated as prior art in the drawings) has a core insulation layer 103 provided with a core wiring conductor 102 extending over the upper and lower surfaces thereof. Buildup insulation layers 104 and buildup wiring conductors 105 are laminated alternately one upon another on the upper and lower surfaces of the core insulation layer 103. A solder resist layer 106 is deposited over the uppermost surface of the laminate.
A plurality of through-holes 107 extend between the upper and lower surfaces of the core insulation layer 103. The core wiring conductor 102 is deposited over the upper and lower surfaces of the core insulation layer 103 and the inner surfaces of these through-holes 107. A resin filler 108 fills the inside of these through-holes 107. A plurality of via holes 109 are formed in the buildup insulation layers 104, respectively. Buildup wiring conductors 105 are formed by deposition on the surfaces of the buildup insulation layers 104 and the inner surfaces of the via holes 109, respectively.
The part of these buildup wiring conductors 105, which is deposited over the buildup insulation layer 104 as the outermost layer on the upper side of the wiring board 120, constitutes wiring pattern portions 105A. These wiring pattern portions 105A are strip-shaped-wiring conductors partly having connection pads 105a for connecting semiconductor elements, which are electrically connected through solder bumps 110 to the electrode terminals of the semiconductor integrated circuit elements 101 by flip-chip bonding. A plurality of the wiring pattern portions 105A are arranged side by side in the shape of a strip.
Among these wiring pattern portions 105A, the semiconductor element connection pads 105a are arranged side by side and exposed from the solder resist layer 106. Electrode terminals 101a of the semiconductor integrated circuit elements 101 are electrically connected through the solder bumps 110 to the exposed connection pads 105a. 
On the other hand, the part of these buildup wiring conductors 105, which is deposited on the buildup insulation layer 104 as the outermost layer on the lower side of the wiring board 120, constitutes wiring pattern portions 105B. These wiring pattern portions 105B have connection pads 105b for external connection to be electrically connected to the wiring conductor of an external electrical circuit board. A plurality of the wiring pattern portions 105B are arranged side by side. Among these wiring pattern portions 105B, the connection pads 105b for external connection are exposed from the solder resist layer 106. The wiring conductor of the external electrical circuit board is electrically connected through solder balls 111 to the exposed connection pads 105a. 
The solder resist layer 106 protects the outermost buildup wiring conductor 105 and defines the connection pads 105a for connecting semiconductor elements and the external connection pads 105b. The solder resist layer 106 can be formed by laminating thermosetting resin paste or film having photosensitivity on the outermost buildup insulation layer 104 provided with the buildup wiring conductor 105, and carrying out exposure and development so as to have openings for exposing the connection pads 105a and 105b, followed by curing.
As shown in FIGS. 13 and 14, the solder resist layer 106 on the upper side has slit-shaped openings 106a for collectively exposing the plurality of side-by-side arranged connection pads 105a. The connection pads 105a in a rectangular shape are defined by partially exposing the wiring pattern portions 105A in the length corresponding to the width of the openings 106a. 
In mounting the semiconductor integrated circuit elements on the wiring board 120 thus configured, firstly, the solder bumps 110 are preformed at the connection pads 105a in order to bring about the engagement between the electrode terminals 101a of the semiconductor integrated circuit elements 101 and the solder bumps 110. Subsequently, the solder bumps 110 are melted by heating, so that the electrode terminals 101a of the semiconductor integrated circuit elements 101 and the connection pads 105a are electrically connected to each other through the solder bumps 110. Thereafter, the semiconductor integrated circuit elements 101 are mounted on the wiring board 120 by applying underfill resin (not shown) composed of thermosetting resin such as epoxy resin into the space between the semiconductor integrated circuit elements 101 and the wiring board 120.
Hereat, to form the solder bumps 110 on the connection pads 105a, in general, paste-like or granular solder is adhered to the surfaces of the connection pads 105a exposed from the solder resist layer 106. This is then heated to melt the solder, so that the melted solder is wet-spread over the exposed surfaces of the connection pads 105a, and solder droplets are formed on the connection pads 105a by the surface tension of the melted solder.
Meanwhile, owing to the recent rapid high integration of the semiconductor integrated circuit elements 101, the pitch between the electrode terminals 101a in the semiconductor integrated circuit elements 101 has become extremely narrow (for example, 50 μm or less). The pitch between the connection pads 105a to which the electrode terminals 101a of the semiconductor integrated circuit elements 101 are connected by flip-chip bonding is correspondingly narrowed (for example, 50 μm or less). Further, there are also demands for an extremely narrow width W1 of the connection pads 105a (for example, 25 μm or less) and for an extremely narrow space W2 between the adjacent connection pads 105a (for example, 25 μm or less) (refer to FIG. 14).
The narrow space W2 between the adjacent connection pads 105a causes the following problem. That is, in the above-mentioned manner that the paste-like or the granular solder is adhered onto the surfaces of the connection pads 105a, and the solder is melted by heating, the melted solder is liable to be connected to the side surfaces of the adjacent connection pads 105a. This causes an electrical short circuit between the adjacent connection pads 105a, making it impossible to perform the normal operation of the mounted semiconductor integrated circuit elements 101.
For example, Japanese Patent No. 3420076 describes the board manufacturing method including the steps of forming solder bumps on connection pads having a large width by continuously forming wiring patterns and the connection pads, the wiring patterns having a smaller width dimension than the connection pads, and exposing the connection pads and the wiring patterns from solder resist, and then adhering the solder onto the exposed connection pads and the exposed wiring patterns, followed by heating to melt the solder. There is a description that this method ensures the formation of the solder bumps on the connection pads having a pitch of 70 to 120 μm.
For further reduction of the pitch between the connection pads (for example, 50 μm or less), even with the above-mentioned method described in Japanese Patent No. 3420076, the melted solder tends to be connected to the side surfaces of the adjacent connection pads, which may cause an electrical short circuit between the adjacent connection pads.
It can be considered that the solder resist layer 106 having independent openings corresponding to a plurality of side-by-side arranged connection pads 105a is disposed so as to individually expose these connection pads 105a. However, when the pitch between the connection pads 105a is narrow and the space between the adjacent connection pads 105a is extremely narrow, it is extremely difficult that the openings for exposing the plurality of side-by-side arranged connection pads 105a with high position accuracy are independently disposed so as to correspond to these connection pads 105a, respectively.
The present applicant has proposed, in Japanese Unexamined Patent Publication No. 2006-344664, the wiring board in which conductive projections, to which the electrode terminals of semiconductor elements are flip-chip bonded, are disposed at a part on strip-shaped wiring conductors for connecting the semiconductor elements, and a solder resist layer is deposited so as to expose the upper surfaces of these conductive projections. In this wiring board, the solder resist layer fills up the space between the adjacent conductive projections, and the side surfaces of these conductive projections are not exposed largely. This suppresses that even when solder bumps are disposed on these conductive projections, the solder is spread over the space between the side surfaces of the adjacent conductive projections.
However, for the wiring board proposed in the above Publication No. 2006-344664, it is necessary to additionally form the conductive projections on the part of the strip-shaped wiring conductors for connecting the semiconductor elements. There remains the problem that the manufacturing steps thereof are complicated and the manufacturing cost thereof is increased.